The present invention relates to a method for fabricating a semiconductor device, more specifically a method for fabricating a semiconductor device fabricating method in which a ferroelectric film is formed by metal organic chemical vapor deposition.
Recently the use of ferroelectric materials as the dielectric films of capacitors is noted. FeRAM (Ferroelectric Random Access Memory) using such ferroelectric capacitors is a prospective nonvolatile memory having characteristics of high speed operation, low electric power consumption, read/write durability, etc.
As materials of such ferroelectric film, ferroelectric materials of layer perovskite structure, PZT (Lead Zirconate Titanate), etc. are noted. To from such ferroelectric film, MOCVD (Metal Organic Chemical Vapor Deposition), which can deposit ferroelectric films on large-area substrates at high speed and with good step covering is noted.
In forming a ferroelectric film by MOCVD, cavities and convexities are formed in the surface of the ferroelectric film due to the crystal structure, etc. with resultant problem of the rough surface morphology. When concavities and convexities are formed in the surface of the ferroelectric film, the concavities and convexities are formed also in the surface of a conduction film formed thereon. When a resist is applied to such conduction film, and light is applied to the conduction film to expose the resist, the incident light is randomly reflected on the concavities and convexities in the surface of the conduction film, which makes it difficult to form patterns with high accuracy.
In trying to solve this problem, insulation film is buried in cavities in the surface of the ferroelectric film to thereby improve the surface morphology (see Patent Reference 1 and Patent Reference 2). Various tries to flatten concavities and convexities in films have been made (see Patent Reference 4, Patent Reference 5 and Patent Reference 6).
The Patent Reference 1 is Specification of Japanese Patent Application Unexamined Publication No. 1994-32613. The Patent Reference 2 is Specification of Japanese Patent Application Unexamined Publication No. 2003-282560. The Patent Reference 3 is Specification of Japanese Patent Application Unexamined Publication No. 2002-170938. The Patent Reference 4 is Specification of Japanese Patent Application Unexamined Publication No. 2002-334970. The Patent Reference 5 is Specification of Japanese Patent Application Unexamined Publication No. 2002-203915. The Patent Reference 6 is Specification of Japanese Patent Application Unexamined Publication No. 2000-340767. The Patent Reference 7 is Specification of Japanese Patent Application Unexamined Publication No. 2002-324894.
However, the method of filling cavities in the ferroelectric film surface with insulation film cannot sufficiently improve the surface morphology and also leaves the insulation film buried in the ferroelectric film surface, and has a problem of deteriorating the characteristics of the ferroelectric capacitor.
The conventional methods for flattening concavities and convexities in the surfaces of films are difficult to apply to flattening the surface of the conduction film of the ferroelectric capacitor.